XC7K420T-2FFG901I - Imirongo Yuzuye, Yashizwemo, Imirima Yateguwe Irembo

Ibyiza
Ibyiza bya FPGAs nibi bikurikira:
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. kwiyongera, ariko bigengwa nibikorwa bya IC bigezweho nibindi bintu).
Ibibi
Ibibi bya FPGAs nibi bikurikira:
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(2) FPGAs irashobora gushyira mubikorwa gusa ibikorwa-bifatika.
Muncamake: FPGAs yishingikiriza kumashanyarazi kugirango ishyire mubikorwa imirimo yose kandi irashobora kugereranwa na chip zabigenewe mubijyanye n'umuvuduko, ariko hariho icyuho kinini muburyo bworoshye bwo gushushanya ugereranije nibikorwa rusange bitunganijwe.

Shushanya indimi na platform

Porogaramu zishobora gukoreshwa ni ibikoresho bitwara ibyuma byerekana imikorere yashyizweho hamwe na tekiniki ya tekinoroji ya porogaramu ikoresheje ikoranabuhanga rya EDA.FPGAs, nkimwe mubikoresho byingenzi bishyira mubikorwa iyi nzira, bireba abakoresha-bayobora, biroroshye cyane kandi bihindagurika, byoroshye gukoresha, kandi byihuse kugerageza no gushyira mubikorwa ibyuma.
Ururimi Ibisobanuro Byururimi (HDL) ni ururimi rukoreshwa mugushushanya sisitemu ya logique ya sisitemu no gusobanura imirongo ya sisitemu, ibyingenzi bikunze gukoreshwa ni VHDL, Verilog HDL, Sisitemu Verilog na Sisitemu C.
Nkururimi rwuzuye rwibisobanuro byururimi, Ururimi rwihuta cyane rwihuta rwuzuzanya rwibikoresho bisobanura Ururimi (VHDL) rufite ibiranga kuba rwigenga rwumuzunguruko wihariye kandi rutagengwa nubushakashatsi, hamwe nibyiza byubushobozi bwagutse bwo gusobanura, ntabwo Biterwa nibikoresho byihariye, hamwe nubushobozi bwo gusobanura igishushanyo mbonera cya logique igenzura muri kode itajenjetse kandi yoroheje, nibindi. Ifashwa namasosiyete menshi ya EDA kandi yakoreshejwe cyane mubijyanye no gushushanya ibikoresho bya elegitoroniki.ikoreshwa cyane.
VHDL ni ururimi rwo murwego rwohejuru rwo gushushanya umuzenguruko, kandi ugereranije nizindi ndimi zisobanura ibyuma, ifite ibiranga ururimi rworoshye, guhinduka no kwigenga bivuye ku gishushanyo mbonera cy’ibikoresho, bigatuma ururimi rusanzwe rusobanura ibyuma bya tekinoroji ya EDA no gukora ikoranabuhanga rya EDA kurushaho bigerwaho kubashushanya.
Verilog HDL ni ururimi rukoreshwa cyane mu gusobanura ibyuma bishobora gukoreshwa mu byiciro byinshi byuburyo bwo gukora ibyuma, harimo kwerekana imiterere, synthesis hamwe no kwigana.
Verilog HDL Ibyiza: bisa na C, byoroshye kwiga kandi byoroshye.Urubanza.Ibyiza mu kwandika ibitera imbaraga no kwerekana imiterere.Ibibi: amakosa menshi ntashobora kugaragara mugihe cyo gukusanya.
VHDL Ibyiza: Syntax ikomeye, urwego rusobanutse.Ibibi: igihe kinini cyo kumenyera, ntabwo gihinduka bihagije.
Porogaramu ya Quartus_II ni uburyo bwuzuye bwo gushushanya ibintu byinshi byakozwe na Altera, bishobora guhuza ibyifuzo bya FPGAs na CPLDs zitandukanye, kandi ni ibidukikije byuzuye kubushakashatsi bwa sisitemu.
Vivado Design Suite, ibidukikije byahurijwe hamwe byashyizwe ahagaragara n’umucuruzi wa FPGA Xilinx muri 2012. Harimo ibidukikije byashushanyije cyane hamwe nigisekuru gishya cyibikoresho kuva kuri sisitemu kugeza ku rwego rwa IC, byose byubakiye ku buryo busangiwe bwamakuru kandi bushingiye ku bidukikije.Suite ya Xilinx Vivado itanga ibikoresho bya IP FIFO ishobora gukoreshwa muburyo bworoshye.